Integrated electronic circuits are usually made with all internal connections set during the manufacturing process. However, because of high development costs, long lead times, and high manufacturing tooling costs of such circuits, users often desire circuits which can be configured or programmed in the field. Such circuits are called field programmable circuits and they can contain programmable links. Programmable links are electrical interconnects which are either broken or created at selected electronic nodes by the user after the integrated device has been fabricated and packaged in order to activate or deactivate the selected electronic nodes.
Programmable links have been used extensively in programmable read only memory (PROM) devices. Probably the most common form of programmable link is a fusible link. When a user receives a PROM device from a manufacturer, it usually consists of an X-Y matrix or lattice of conductors or semiconductors. At each cross-over point of the lattice a conducting link, call a fusible link, connects a transistor or other electronic node to this lattice network. The PROM is programmed by blowing the fusible links to selected nodes and creating an open circuit. The combination of blown and unblown links represents a digital bit pattern of ones and zeros signifying data which the user wishes to store in the PROM. By providing an address the data stored on a node may be retrieved during a read operation.
In recent years, a second type of programmable link, call an anti-fuse link, has been developed for use in integrated circuit applications. Instead of the programming mechanism causing an open circuit as in the case with fusible links, the programming mechanism in an anti-fuse circuit creates a short circuit or relatively low resistance link. Thus the anti-fuse link presents an open circuit prior to programming and a low resistance connection after programming. Anti-fuse links consist of two electrodes comprised of conductive and/or semiconductive materials and having some kind of a dielectric or insulating material between them. During programming, the dielectric at selected points in between the conductive materials is broken down by predetermined applied voltages, thereby electrically connecting the conducting and/or semiconducting materials together.
A plurality of such anti-fuses may be disposed in a semiconductor integrated circuit, and may be selectively blown to create low impedance interconnects at selected locations within the integrated circuit. The anti-fuses may be blown either before or after packaging of the integrated circuit die.
Critical issues facing the designer of the anti-fuse device is the capability to program the device using a low potential while minimizing leakage currents. The two basic circuit configurations for the anti-fuse element are shown in FIGS. 1 and 2. In both configurations a transistor is serially connected to the anti-fuse element. In the configuration shown in FIG. 1, the anti-fuse 5 is connected to a reference potential and the transistor 10 is connected to a supply potential. There is a transistor source bias associated with this approach which requires a higher supply potential than would be required if there were no transistor source bias. In the configuration shown in FIG. 2, the anti-fuse 15 is connected to a supply potential and the transistor 20 is connected to a reference potential. The circuit of FIG. 2 is much easier to program than the circuit of FIG. 1 due to the elimination of the transistor source bias associated with the approach depicted in FIG. 1. Elimination of the source bias allows the anti-fuse element to be programmed using a lower potential. However, it has been observed that leakage current is increased between the supply potential at supply node 25 and the reference potential at reference node 30, and/or that leakage current is increased between supply node 25 and the substrate. This leakage is not desirable in the programmable circuit for it increases the standby current.
Post program transistor current-voltage curves are shown in FIG. 3. The drain voltage has been increased from 0 V to 5 V in 1 volt increments with the resultant drain current measured and plotted at each increment. The solid lines represent the data plotted for FIG. 2 and the dashed lines represent the data plotted for FIG. 1. The curves have been lettered. The solid lines are represented by a letter having no prime symbol and the dashed lines are represented by a letter having a prime signal. Each of the curves having corresponding letters have the same gate voltage. For example F and F' had a gate voltage of 0 V. It can be clearly seen that when the supply node 25 is the drain of the transistor, as shown in FIG. 2, the leakage current for V.sub.g =0 is too large for the transistor to handle, see curve F. Conversely, if we were to use reference node 35 as the transistor source and the supply node 40 as the transistor drain, as shown in FIG. 1, the transistor leakage at V.sub.g =0 is much lower, see curve F'. However as was discussed earlier, the configuration of FIG. 1 has a transistor source bias which requires a higher supply potential than the circuit of FIG. 2. Therefore a need exists to minimize leakage current while providing a low programming potential.